module KB_Datapath(PC, iClk);
  input [31:0] PC;
  input iClk;
  wire [31:0]tPC, wt1PC;
  wire[31:0] Inst, wISE;
  wire wRegDst, wRegwrite, wALUSrc, Zout, wSel;
  wire [7:0] wRead1, wRead2, wALU2, wALUResult, wReadDM;
  wire [2:0] wALUControl;
  wire [31:0] wJumpAddress, wALUResult2;
  
  assign tPC=PC;
  
  InstMemory Im1(PC, iClk, Inst);
  
  ControlUnit Cu1(Inst, wRegDst, wJump, wBranch, wMemRead, wMemtoReg, wALUOp, wMemWrite, wALUSrc, wRegWrite);
  MUX_2x1_5bit Mux1(Inst[20:16], Inst[15:11], wRegDst, wWriteRegister);
  Register Reg1(Inst[25:21], iClk, wRegWrite, wWriteRegister, wWriteData, wRead1);
  Register Reg2(Inst[20:16], iClk, wRegWrite, wWriteRegister, wWriteData, wRead2);
  
  Sign_Extended SE1(Inst[15:0], wISE);
  MUX_2x1_8bit Mux2(wRead2, wISE[7:0], wALUSrc, wALU2);
  // wISE 32bit?? ????? ?? ?? ??? ????? ????...
  ALUControl AC1(ALUOp, wALUControl);
  ALU_8bit ALU1(wRead1, wALU2, wALUControl, wALUResult, Zout);
  
  DataMemory DM1(wALUResult, wRead2, wMemWrite, wMemRead, iClk, wReadDM);
  MUX_2x1_8bit Mux3(wReadDM, wALUResult, wMemtoReg, wWriteData);
  
  Full_Adder F1(tPC, 32'b00000000000000000000000000000100, wt1PC);
  
  Left_Shift2 LS1({6'b000000,Inst[25:0]}, {4'b0000,wJumpAddress[27:0]});
  assign wJumpAddress[31:28]=wt1PC[31:28];
  
  Left_Shift2 LS2(wISE, wISELS);
  ALU_32bit ALU2(wt1PC, wISELSE, 3'b010, wALUResult2);
  and a1(wSel, wBranch, Zout);
  MUX_2x1_32bit Mux4(wt1PC, wALUResult2, wSel, wt);
  MUX_2x1_32bit Mux5(wt, wJumpAddress, wJump, wtp1PC);
  
  assign wPC=wtp1PC;
  
endmodule